Integrated circuits consist of multiple logic circuit elements that each have a power consumption requirement. These logic circuit elements are normally formed on the integrated circuit by an integrated circuit (IC) fabrication system that uses software code and/or data that provides representations of the logic circuit elements which the IC fabrication system may use to position and provide given logic circuit elements at the appropriate point on the IC based on a design. Such logic circuit elements are referred to as “cells,” “logic cells” or “standard cells,” and are used as basic building blocks of an overall IC architecture. An example software code, having executable instructions, used to create such logic cells is the hardware description language (HDL). Also “netlist” languages may be used to specify logic cells and corresponding circuit connectivity on computer-aided design (CAD) systems. In any case, logic cells are small building blocks (i.e. up to about 30 to 40 transistors) that are usually stored in libraries that may be drawn upon to create circuit designs on an IC.
Various techniques and approaches exist for reducing power consumption on integrated circuits. For example, portions of the clock tree within the IC may be gated or switched off by control modules that monitor activity of “logical areas” on the IC, that is, areas that perform a given logical function.
Many logic circuits such as flip-flops and latches employ an individual clock input, that is obtained from the IC clock tree, that switch various states of the logic circuit when an appropriate input is received, such as “set,” “reset,” etc. There are periods of time however, when a logic circuit may remain in a given logic state, such as, for example, a set mode or a reset mode, where the clock signal is not specifically needed. In existing designs, spurious toggling may occur at various internal nodes of the logic circuit that receive inputs from the clock, and also other nodes that are not directly controlled by the clock, when the logic circuit is in such a given mode such as set or reset mode. Such toggling needlessly consumes power and serves no useful purpose within the integrated circuit. In other words, even in an IC that utilizes known power consumption reduction techniques, such as switching portions of the clocking tree on and off in logical areas that have no activity, the individual logic circuits formed by cells will still continue to waste power during activity of logical areas due to needless toggling.
FIG. 1 illustrates known logic cell 150, (also known as a “standard cell” or as a “cell”), of an integrated circuit (IC). The logic cell 150 includes logic circuitry 100 which may be, for example, a latch logic circuitry. The logic circuitry includes a set 101 input, a data (“D”) 103 input, and receives a clock input from the IC clock tree, CLK 111. The logic cell 150 includes a clocking circuitry portion that divides the CLK 111 into a internal clock signal “c” 107, and an internal negated clock input labeled “cn.” The c 107 and cn 109 inputs are provided to various nodes within the logic circuitry portion 100 of the logic cell 150.
FIG. 2 illustrates a more detailed example of a known logic cell 200. Logic cell 200 includes a latch logic circuitry portion that is exemplary of the known logic circuitry portion 100. The latch logic circuitry portion of the logic cell 200 includes a clocked inverter 201 which provides an inverted D 103 input to NAND gate 203. The NAND gate 203 provides output to inverters 205 and 207, with inverter 207 providing the latch output “Q” 105. The NAND gate 203 also provides a feedback output to clocked inverter 209, which receives the negated clock cn 109. The prior clocking circuitry portion 113 of the logic cell 200 consists of two inverters 115 and 117. The internal negated clock signal cn 109 is taken from the first inverter 115 and the internal regular clock signal c 107 is taken from the second inverter 117. When the logic cell 200 is in a given logic state, such as a set mode, the nodes formed by clocked inverters 201 and 209 will continue to receive their respective clock signals which results in unnecessary power consumption.
In FIG. 2, when set 101=0, the output Q 105=1. However, all clock nodes toggle while the latch logic circuitry portion of the logic cell 200 remains in the set mode. Further, the node “qf_x” may continuously toggle in the set mode whenever D is in a low condition. Also, four logic gates are required on the path from D 103 to Q 105, that is, clocked inverter 201, NAND gate 203, inverter 205 and inverter 207. The area on the integrated circuit to implement the known logic cell 200 requires 20 transistors such as 20 field effect transistors (FETs).
FIG. 3 illustrates another example logic cell 300 that exhibits similar problems with respect to undesirable toggling. A flip-flop logic circuitry portion of the logic cell 300 uses the same configuration of clocking circuitry portion as discussed with respect to FIG. 2. A negated clocked (cn) inverter 301 provides input to NAND gate 303 which in turn provides output to a clocked transmission gate 311. The transmission gate 311 provides output to inverter 305 which in turn feeds inverter 307 which provides output Q 105. NAND gate 315 receives set 101 input and a second input from inverter 305, and feeds negated clocked transmission gate 313, which in turns provides feedback to inverter 305. The NAND gate 303 receives the set 101 input and its output provides a feedback input loop back to itself from clocked inverter 309. The clock nodes of the flip-flop portion of logic cell 300 also toggle undesirably, thereby consuming power needlessly.